1. Field of the Invention
The present invention relates to a semiconductor memory device, and a method of checking the semiconductor device and a method of using the same, and more specifically to a semiconductor memory device having an error detection/ correction function, and a method of checking the semiconductor memory device and a method of using the same.
2. Description of the Related Art
Conventionally, a semiconductor device often includes an error checking and correcting circuit (hereinafter referred to ECC.) other than a semiconductor memory for storing data. Japanese Patent Laid-Open Publication No. Hei01-209552 discloses such a semiconductor memory device. In accordance with the semiconductor device, even if any error happens in data upon write and read operation of the data, the semiconductor memory device checks the data and corrects the error in itself to improve reliability thereof.
FIG. 10 illustrates an example of such a semiconductor device as the type described above. The semiconductor memory device includes an address register 101, a write data register 102, an error correction code generation circuit 103, a memory circuit 104, a changeover circuit 105, an error detection circuit 106, an error detection flag register 107, an error correction circuit 108, a read data register 109, and a test mode register 110.
The semiconductor memory device includes an external device (not shown) connected thereto through a bus (not shown) connected with the address register 101, the write data register 102, the error detection flag register 107, the read data register 109, and the test mode register 110.
When the external device connected with the semiconductor memory device writes data in the memory circuit 104, a signal indicative of an ordinary mode is applied to a test mode register 110. The test mode register 110 after receiving the signal applies it to the switching circuit 105 as a control signal. The switching circuit 105 after receiving the control signal h2 indicative of the foregoing signal, it connects the memory circuit 104 to the error detection circuit 106 and the error correction circuit 108.
Thereafter, the external device applies the data to be written in the memory circuit 4 to the write data register 102. The write data register 102 after receiving the data applies the data to the error correction code generating circuit 103. The error correction code generation circuit 103 generates an error correction code for the foregoing data. Thereafter, the error correction code generation circuit 103 applies the generated error correction code to the foregoing data, and sends it to the memory circuit 104 as write data h3.
Upon writing data the external device applies a signal indicative of an instruction of read operation and of address. The address register 101 after receiving the foregoing signal applies it to the memory circuit 104 as an address signal h1. The memory circuit 104 after receiving the address signal hi stores write data h3 in an memory area corresponding to an address indicated by the address signal h1. Upon reading the data the external device applies the signal indicative of an instruction of read operation and of an address to the address register 101. The address register 101 after receiving the foregoing signal applies it to the memory circuit 104 as the address signal h1. The memory circuit 104 after receiving the address signal h1 reads the data from a memory area corresponding to the address indicated by the address signal h1, and sends the data to the switching circuit 105 as read data h4. The switching circuit 105 sends the read data h4 received from the memory circuit 104 to the error detection circuit 106 and the error correction circuit 108.
The error detection circuit 106 judges based upon an error correction code added to the read data h4 whether or not any error is existent in the red data h4. If the read data h4 has any error, then the error detection circuit 106 sends a flag indicative of error detection to the error detection flag resistor 107. The error detection flag register 107 holds the foregoing flag and informs the outside of happening of any error.
Simultaneously, the error detection circuit 106 sends a detection result indicative of the detection of any error to the error correction circuit 108. The error correction circuit 108 corrects the error in the read data h4 based upon the detection result. Thereafter, the error correction circuit 108 sends the read data h4 subject to the error correction to the read data register 109.
FIG. 11 illustrates such an error detection circuit 106 and an error correction circuit 108. The illustrated error detection circuit 106 and error correction circuit 108 checks presence of any error, the number of error bits, position of any error bit based upon a parity check matrix H represented by a formula 1. The error detection circuit 106 includes a syndrome generation circuit 106-1 and a syndrome decode circuit 106-2 as illustrated in FIG. 11.                     H        =                  ❘                      xe2x80x83                    ⁢                                                                      0                                                  1                                                  1                                                  1                                                  1                                                  0                                                  0                                                                              1                                                  0                                                  1                                                  1                                                  0                                                  1                                                  0                                                                              1                                                  1                                                  0                                                  1                                                  0                                                  0                                                  1                                                      ⁢                          xe2x80x83                        ❘                                              (        1        )            
The syndrome generation circuit 106-1 is to generate a syndrome value using the read data h4, an example of which is illustrated in FIG. 12. The syndrome generation circuit 106-1 includes EXOR (exclusive or) 106A to 106J. When the read data h4 comprises bits x0 to x6, the syndrome generation circuit 106-1 calculates syndrome values s0, s1 and s2 using the following formula. In the read data h4, x0 to x3 are information bits corresponding to the data, and x4 to x6 inspection bits corresponding to the error correction code.
s0=x1*x2*x3*x4
s1=x0*x2*x3*x5
s2=x0*x1*x3*x6
Herein, a code xe2x80x9c*xe2x80x9d in the foregoing formulae represents logical sum. Thereafter, the syndrome generation circuit 106-1 outputs the calculated syndrome values s0, s1 and s2 from EXOR gates 106C, 106F and 106J to the syndrome decode circuit 106-2.
The syndrome decode circuit 106-2 decodes the syndrome values s0, s1 and s2 and calculates the presence of any error, the number of error bits and the position of the error bit, and so on. The syndrome decode circuit 106-2 includes inverters 106K to 106M, a NOR gate 106N, an inverter 106P and NAND gates 106Q to 106T.
The syndrome decode circuit 106-2 after receiving the syndrome values s0, s1 and s2 outputs an error detection signal EF as the foregoing flag from the inverter 106P using the following formulae and simultaneously generates bits y0 to y6 using the following formula together with the error correction circuit 108 including the EXOR gates 108A to 108D.
y0=x0*((xe2x88x92s0)xc2x7s1xc2x7s2)
y1=x1*(s)xc2x7(xe2x88x92s1)xc2x7s2)
y2=x2*(s0xc2x7s1xc2x7(xe2x88x92s2)
y3=x3*(s0xc2x7s1xc2x7s2)
y4=x4*(s0xc2x7(xe2x88x92s1)xc2x7(xe2x88x92s2))
y5=x5*((xe2x88x92s0)xc2x7s1xc2x7(xe2x88x92s2))
y6=x5*((xe2x88x92s0)xc2x7(xe2x88x92s1)xc2x7(xe2x88x92s2))
EF=s0+s1+s2
In the foregoing eight formulae, a code xe2x80x9cxe2x88x92xe2x80x9d represents logical inversion and a code xe2x80x9c+xe2x80x9d represents logical sum. In FIG. 12 an error correction circuit for bits y4 to y6 corresponding to check bits x4 to x6 is omitted.
The error detection circuit 106 sends the foregoing flag generated as such to the error detection flag register 107. If there is no error, then the foregoing flag indicates xe2x80x9c0xe2x80x9d while if there is any error, then the foregoing flag indicates xe2x80x9c1xe2x80x9d. The error correction circuit 108 sends the generated bits y0 to y3 to the read data register 109 as the read data h4. Such an error correction code generation circuit 103, error detection circuit 106 and error correction circuit 108 constitute the ECC circuit.
For checking whether or not the error detection/correction function of the ECC circuit operates normally the foregoing external device diagnoses any trouble of the ECC circuit. Upon diagnosis of the trouble of the ECC circuit the external device applies the control signal h2 indicative of a test mode to the switching circuit 105 through a test mode register 110. The changeover circuit 105 after receiving the control signal h2 of the test mode separates the memory circuit 4 and connects the error correction code generation circuit 103 to the error detection circuit 106 and the error correction circuit 108.
Thereafter, the external device once applying write data containing error and write data not containing error to the write data register 102, the write data is applied to the error detection circuit 106 and the error correction circuit 108 after passage through the error correction code generation circuit 103 and the changeover circuit 105. Operation of the error detection circuit 106 and the error correction circuit 108 is clarified on the basis of the flag of the error detection flag and data of the read data register 109.
Hereby, the external device compares data applied to the write data register 102 and data from the read data register 109 with each other and checks whether or not the error detection/correction function of the ECC circuit composed of the error correction code generation circuit 103, error detection circuit 106 and error correction circuit 108 based upon the value of the flag in the error detection flag register 107.
The prior art illustrated in FIG. 10 however suffers from the following problems: The external device applies the control signal h2 indicative of the ordinary mode and the test mode to the changeover circuit 105 in order to control the changeover operation of the changeover circuit 105. For this, the aforementioned prior semiconductor memory device has a trouble that there is required generation means for generating the control signal h2. The semiconductor memory device has also another trouble that there is required the test mode register 110 for applying the control signal h2 to the changeover circuit 105.
The present invention has been made to solve the aforementioned problems of the prior art, and has an object to provide a semiconductor memory device capable of simplifying changeover between an ordinary mode and a test mode and of shortening test time for an error detection and error correction function, and further provide a method of checking the semiconductor memory device and a method of using the same.
To achieve the foregoing object, a semiconductor memory device, according to a first aspect of the present invention, is featured by comprising: a memory part which includes m memory areas (m is an arbitrary natural number, same in the following.) each for storing data for writing and reading data into and from a memory area designated by an input address signal, the memory part including m memory areas each for storing data; a code tagging section for tagging a code for checking any error of the data to the input data and sending the data to which the code is tagged to the memory section; a changeover section for outputting the data from the memory section when the address signal designates the memory area of the memory part and outputting the data from the code tagging section when the address signal does not designate the memory area of the memory section; and an error processing section for checking the presence of any error of the data based upon the code tagged to the data when the data from the changeover section, and correcting an error when the error is detected and outputting the data.
A semiconductor memory device, according to a second aspect of the present invention, is featured by comprising a memory section which includes p memory parts among n memory areas set as memory parts for writing and reading data into and from a memory area designated by an input address signal after the input address signal designates the memory part, a code tagging section for adding a code for checking any error in input data to the input data and sending the data to which the code is tagged to the memory part; a changeover section for outputting the data from the memory section when the foregoing address signal designates a memory area in the memory part, and further outputting the data from the code tagging section when the foregoing address signal doe not designate the memory area in the memory part; and an error processing section for checking presence of any error in the data based upon the code tagged to the data after receiving the data from the changeover section, and correcting when any error is detected, the error and outputting the same.
A semiconductor memory device, according to a third aspect of the present invention, is that described in the first and second aspects, and is featured by further comprising a bypass section for permitting the data inputted into the code tagging section to bypass the code tagging section; and a bypass changeover part interposed between the code tagging section and the memory part for sending the data from the code tagging section the data from the bypass section to the memory section in response to the input changeover signal.
A semiconductor memory device, according to a fourth aspect of the present invention, is featured by comprising: a memory part for writing and reading data with the aid of an input address signal; a code tagging section for tagging a code for checking any error in input data to the input data, and outputting the data to which the code is tagged; a bypass section for permitting the data inputted into the code tagging section to bypass the code tagging section; a bypass changeover section for sending the data from the code tagging section or the data from the bypass section to the foregoing memory section in response to an input first changeover signal; and an error processing section for checking, as receiving the data from the memory section when an input second changeover signal indicates an error processing, presence of error in the data based upon the code tagged to the data, and correcting, when any error is detected, the error and outputting the data, and, when the input second changeover signal indicates release of the error processing, outputting the data received from the memory section as it is.
A semiconductor memory device, according to a fifth aspect of the present invention, is featured by comprising: a memory part which includes m memory areas each for writing and reading data into and from a memory area designated by an input address signal; a code tagging section for adding a code to check error in input data to the input data, and outputting the data to which the aforesaid code is added; a bypass part for permitting the data inputted to the code tagging section to bypass the aforesaid code tagging section: a bypass changeover section for sending the data from the code tagging section or the data from the bypass section to the memory section in response to an input first changeover section; a changeover section for outputting the data from the memory section when the address signal designates a memory area in the aforesaid memory section while outputting the data from the bypass changeover section when the address signal does not designate the memory area of the aforesaid memory section; an error processing section for checking, after receiving data from the aforesaid changeover section when an input second changeover signal indicates an error processing, presence of any error in the data based upon the code tagged added to the data, and when any error is detected, correcting the error and outputting the data while, when the input second changeover signal indicates release of the error processing, outputting the data received from the changeover section as it is.
A semiconductor memory device, according to a sixth aspect of the present invention, is featured by comprising: a memory section, which includes p memory parts with n memory areas taken as each memory part, for writing and reading, after an input address signal designates the memory part, data into the memory area designated by the address signal; a code tagging section for tagging a code to check error in input data to the input data, and outputting the data to which the code is tagged to a bypass section for permitting the data inputted into the code tagging section to bypass the code tagging section; a bypass changeover section for sending the data from the code tagging section or the data from the bypass section to the memory section in response to an input first changeover signal; a changeover section for outputting the data from the memory section when the address signal designates a memory part of the memory section while outputting the data from the bypass changeover section when the address signal does not designate the memory part of the memory section; and an error processing section for checking, after receiving the data from the changeover section when an input second changeover signal indicates an error processing, presence of any error in the data based upon the code tagged to the data, and when any error is detected, correcting the error and outputting the data while the inputted second changeover signal indicates release of the error processing, outputting the data received from the changeover section.
A method of checking a semiconductor memory device described in the first aspect, according to a seventh aspect of the present invention, is featured by comprising: a first step of applying an address signal that does not designate a memory area of the aforesaid memory section to the aforesaid changeover section; a second step of applying checking data to the aforesaid code tagging section after the first step is completed; and a third step of judging whether the aforesaid code tagging section and the aforesaid error processing section are good or not by comparing, after receiving the data outputted by the error processing section in response to the data inputted in the second step, the just mentioned data with the data used in the second step.
A method of checking a semiconductor memory device described in the second aspect, according to an eighth aspect of the present invention, is featured by comprising: a first step of applying an address signal not designating the memory area of the aforesaid memory section to the aforesaid changeover section; a second step of applying checking data to the aforesaid code addition section after the first step is completed; and a third step of judging whether the aforesaid code addition section and the aforesaid error processing section are good or not by comparing, once receiving data outputted by the aforesaid error processing section in response to the data inputted by the aforesaid second step, the just mentioned data with the data used ion the second step.
A method of checking a semiconductor memory device described in the third aspect, according to a ninth aspect of the present invention, is featured by comprising: a first step of applying an address signal not designating the memory area of the aforesaid memory section to the aforesaid changeover section, and further applying a changeover signal instructing bypass to the aforesaid bypass changeover section; a second step of applying checking data to the aforesaid code tagging section after the first step is completed; a third step of comparing, after receiving data outputted from the aforesaid error processing section in response to the data inputted by the second step, the just mentioned data with the data used in the second step; a fourth step of applying a changeover signal instructing release of the bypass to the aforesaid bypass changeover section after the third step is completed; a fifth step of applying checking data to the aforesaid code tagging section after the fourth step is completed; and a sixth step of judging whether the aforesaid code tagging section is good or not by comparing, once receiving the data outputted from the aforesaid error processing section in response to the data inputted by the fifth step, the just mentioned data with data used in the fourth step.
A method of checking a semiconductor memory device described in the fourth aspect, according to a tenth aspect of the present invention, is featured by comprising: a first step of applying a first changeover signal instructing bypass to the bypass changeover section, and further applying a second changeover signal indicative of error processing to the error processing section; a second step of applying checking data to the code addition section after the first step is completed; a third step of judging whether the aforesaid error processing section is good or not by comparing, once receiving the data outputted from the error processing section in response to the data inputted by the second step, the just mentioned data with the data used in the second step; a fourth step of applying a changeover signal instructing release of bypass to the bypass changeover section after the third step is completed; a fifth step of applying checking data to the code tagging section after the fourth step is completed; and a sixth step of judging whether the aforesaid code tagging section is good or not by comparing, once receiving the data outputted from the error processing section in response to the data inputted by the fifth step, the just mentioned data with the data used in the fourth step.
A method of checking a semiconductor memory device described in the fifth aspect, according to an eleventh aspect of the present invention, is featured by comprising: a first step of applying an address signal not designating the memory part of the memory section to the changeover section, and applying a first changeover signal instructing bypassing to the changeover section, and further applying a second changeover signal indicative of error processing to the error processing section; a second step of applying checking data to the code tagging section after the first step is completed; a third step of judging whether the aforesaid error processing section is good or not by comparing, after receiving data outputted from the error processing section, the just described data with the data used in the second step; a fourth step of applying a changeover signal instructing release of bypassing to the aforesaid bypass changeover section after the third step is completed; a fifth step of applying checking data to the code tagging section after the fourth step is completed; and a sixth step of judging whether the aforesaid code tagging section is good or not by comparing, after receiving the data outputted from the aforesaid error processing section, the just described data with the data used in the step 4, in response to the data inputted by the fifth step.
A method of checking a semiconductor memory device described in the sixth aspect, according to the twelfth aspect of the present invention, is featured by comprising: a first step of applying an address signal not designating a memory part in the aforesaid memory section to the aforesaid changeover section, and applying a first changeover signal instructing bypassing to the aforesaid bypass changeover section, and further applying a second changeover signal indicative of error processing to the aforesaid error processing section; a second step of applying checking data to the aforesaid code tagging section after the first step is completed; a third step of judging whether the aforesaid error processing section is good or not by comparing, after receiving data outputted from the aforesaid error processing section, the data with the data used in the second step, in response to the data inputted by the second step; a fourth step of applying a changeover signal instructing release of bypassing after the third step is completed; a fifth step of applying checking data to the aforesaid code tagging section after the fourth step is completed; and a sixth step of judging whether the code tagging section is good or not by comparing, after receiving data outputted from the aforesaid error processing section, the data with the data used in the fourth step, in response to the data inputted by the fifth step.
A method of using a semiconductor memory device described in the fourth aspect, according to a thirteenth aspect of the present invention is featured by a fact that data is written and read into and from the aforesaid memory section by applying the first changeover signal instructing release of bypassing to the aforesaid bypass changeover section, and further applying the second changeover signal instructing release of the error processing.
A method of using a semiconductor device described in the fifth aspect, according to a fourteenth aspect of the present invention, is featured by a fact that data is written and read into and from the aforesaid memory section by applying a first changeover signal instructing release of bypassing to the aforesaid bypass changeover section, and further applying a second changeover signal instructing release of the error processing to the aforesaid error processing section.
A method of using a semiconductor memory device described in the sixth aspect, according to a fifteenth aspect of the present invention is featured by a fact that data is written and read into and from the aforesaid memory section by applying a first changeover signal instructing release of bypassing to the aforesaid bypass changeover section, and further applying a second changeover signal instructing release of error processing to the aforesaid error processing section.